1. Field of the Invention
The invention relates generally to the semiconductor power devices. More particularly, this invention relates to an improved and novel device manufacturing process to provide asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) with Schottky barrier source implemented with low-barrier height rare earth metal silicide for a best drive current without subject to a limitation of the high temperature processes and meanwhile providing low contact resistance of source and body contacts, which is achieved through silicided contact on the entire mesa area totally insulated from the trenched gates covered under an insulated spacer.
2. Description of the Prior Art
It is known in the semiconductor power industry to implement a Schottky barrier source or metal silicide source electrode to overcome the parasitic bipolar conduction in a DMOSFET device. In order to prevent an unclamped inductor switching (UIS) in the semiconductor power device, it is necessary to reduce the parasitic bipolar conduction. With the implementation of Schottky barrier source the theoretical emitter efficiency at the source is reduced by orders of magnitude compared to the conventional silicon source junction structures. Such configuration can significantly eliminate the parasitic bipolar gain of the device. However, conventional manufacturing processes are still limited by the use of metals of high barrier height. The devices as now available to those of ordinary skill in the art therefore suffers low drive current and subject to potential increased body bias and reducing the gate drive or even forward bias the body-source junction and initiate a snapback.
U.S. Pat. No. 4,675,713 discloses a method of using the source Schottky junction as the body contact for a semiconductor power device as shown in FIG. 1A. In FIG. 1A, the diffused channel of the MOS transistor is of the type in which contact to the drain region 22 is made from the back side of the semiconductor device. Channel regions 24 are formed by diffusing P type body regions 41 into selected portions of the surface of an N type wafer. Source regions are then formed by diffusing a heavily doped N+ region into the P type body region to form a rectifying N+P junction. Specifically, the source regions 60 of the device are formed, not by diffused N type regions, but by a low minority carrier injecting metal having a low barrier height with respect to the P type channel region. Channel region 24 is the surface portion of body region 41 located between source and drain and controlled by potential on gate electrode 26 connected to a gate electrode 30 and padded with an gate oxide layer 28 underneath. The patented disclosure uses a low minority carrier injecting source region. A metal silicide layer is, implemented to form the low minority carrier injection source region. The metal silicide source provides a source of majority carriers and meanwhile reducing the minority carrier injection and hence reducing the parasitic bipolar transistor action. However, the higher barrier height of the source contact can potentially increase the body bias and reduce the gate drive, or even increase the forward bias of the body-source junction and initiate a snapback
U.S. Pat. No. 4,983,535 discloses a fabrication method to manufacture a DMOS device shown in FIG. 1B. An N+ type silicon wafer 10 supports an N type epitaxial layer 11 thereon. A masking oxide 20 is either grown or deposited on top of the epitaxial layer. A photolithographic mask is used to create a hole in oxide 20. The resist is then removed and a heavily doped P+ region 23 is diffused into epitaxial layer 11. A second P-type diffusion creates the body region 25. A metal layer 27 is deposited on the silicon surface. This metal is a refractory metal such as tungsten applied by a selective deposition process. The metal is selected to form a suitable Schottky barrier with the silicon. As such it serves as a source of electrons for the DMOS device. Then using refractory metal layer 27 as an etch mask, the remnant of oxide 26 is removed and a trench (or groove) etched into the silicon to define the DMOS transistor gate. The wafer is then subjected to thermal oxidation and a gate oxide 29 is grown on the exposed silicon. A layer of polysilicon 32 is deposited over the wafer. This layer is doped to render it conductive either during or after deposition. Polysilicon 32 is then etched so as to remove it except for that portion inside the trench. Then the exposed surface of polysilicon 32 is oxidized so that it forms an insulating layer over the conductive plug facing oxide layer 29. Thus, the remaining plug of polysilicon forms the insulated DMOS gate electrode. A connection thereto is shown schematically at 33. A conventional metallization layer 34 is applied over the wafer and etched back. This makes an electrode contact to refractory metal layer 27 and to deep P+ regions 23 and thereby forms source contact 55 which is shown schematically. N+ wafer 10 forms the DMOS drain contact shown schematically at 36. The method includes the processing steps use a starting material of a heavily doped silicon wafer, which has an epitaxial layer thereon. A DMOS body region is diffused into the epitaxial layer and a deep body contact region created. The source is a refractory metal Schottky barrier located on top of the body region. A trench is etched into the epitaxial layer so as to fully penetrate the body region and the trench surfaces oxidized to form a gate oxide. The trench is then filled with doped polysilicon to create a gate electrode. The resulting DMOS has a relatively short channel and the parallel bipolar parasitic transistor cannot be turned on. Since the method forms the Schottky barrier source prior to the trench and gate formation, therefore only refractory metal with high barrier height can be used. For this reasons, the device suffers a low drive current.
Therefore, a need still exists in the art of power semiconductor device design and manufacture to provide new manufacturing method and device configuration in forming the power devices such that the above discussed problems and limitations can be resolved.